1. Field of the Invention
The present invention relates to a variable length code processor that performs variable length encoding and decoding.
2. Description of the Background Art
As technology for digital is advanced, it is improved to digitize processes for which analog process has been usually employed. Its typical representative is, for example, time-varying image processes, e.g., MPEG2. In such a filed, data compression technology is important, and the variable length encoding and decoding of data is one of useful techniques.
Unfortunately, due to a vast difference between the processing contents of a variable length encoding and that of a variable length decoding, it has been the general practice to perform a variable length encoding and a variable length decoding by using a unit for the former and a unit for the latter in the inherent encoding standard, respectively.
Since the conventional variable length encoding and decoding processes have been made in the above-mentioned manner, it has been impossible for a single unit to perform efficient variable length encoding and decoding processes in a plurality of encoding standards.
JP-A-5-56283 (1993) discloses an encoding and decoding equipment in which an encoding table and a decoding table are housed in one memory (ROM) so that encoding and decoding processes are carried out by the software process of the same CPU.
Improvement on the hardware in this encoding and decoding equipment is such a degree that both the encoding table and decoding table are stored in a single ROM. Therefore, it is merely a configuration in which a variable length encoding equipment and a variable length decoding equipment are substantially united. Also, little or no attempt is made to simplify hardware configuration.